The present invention relates to memory controllers for use in microcomputer systems incorporating commercially available microprocessor chip sets. In particular, this invention relates to microcomputers in which an asynchronous memory controller is used to access the system memory asynchronously with respect to the operational speed of the microprocessor chip set. Memory controllers generally provide control signals for writing data to and reading data from system memory.
Microprocessor and memory chip sets are advancing rapidly and are expected to continue to advance indefinitely. Moreover, microprocessor and memory chip sets are advancing at different rates so that the difference in performance parameters, particularly operational speed, of the microprocessor, the memory and the bus over which they typically communicate tends to expand or contract, i.e., become greater or lesser, as advances are perfected. In addition, performance characteristics of microcomputers chip sets employing emerging technologies also advance at different rates.
While present-day microcomputer manufacturers have control over the design and configuration of the systems they produce, they typically must anticipate the parameters necessary for compatibility of their system with new microprocessors and memory devices, as well as add-on peripherals, accessories and memory options produced by other manufacturers. The performance and interface characteristics of microprocessors and memory devices often vary substantially from one release of the same device to the next; similarly such characteristics of peripherals, accessories and memory options will vary among the manufacturers of these devices.
While the performance characteristics of peripheral devices are often designed for less than optimum performance, i.e., "detuned" to accommodate variations in microcomputer system designs, microprocessor chip and memory devices are not usually so detuned. Therefore, the manufacturer of high performance microcomputers must allow for different, even inferior, performance characteristics of peripheral and accessory devices and some memory options in order to produce a system which is compatible with the maximum number of devices attachable to the system. In addition, the microcomputer manufacturer must anticipate upgrades and changes of microprocessor chip sets and memory devices. If the microcomputer manufacturer does not so anticipate such upgrades, it will limit the marketability of the system to less than the total market available for his product.
A complete microcomputer, which is often intended for desktop applications, includes subsystems such as a central processing unit (hereafter referred to as the "CPU", "processor" or "microprocessor"), a math "coprocessor", DMA capabilities, memory, miscellaneous system ports, and interfaces to video, keyboard, floppy disks, serial and parallel ports, scsi devices, and a mouse pointing device.
The microcomputer functions by manipulating address, data, and control signals among the subsystems within the system. The control data flow into and out of system memory is provided by a memory controller which usually controls the data flow and timing between the processor, main system memory, and the bus.
As faster microprocessor and memory devices became available to microcomputer system designers, increased performance was limited by other components of the systems. For example, the speed of memory controller technology could not be expected to increase at a rate commensurate with the increasing speed of the microprocessor and memory devices, especially as the relative operation of microprocessors and memory devices is changed and changed at different rates.
If the memory controller were simply driven faster to take advantage of the faster microprocessors and memory devices now becoming available, certain memory devices would begin to fail in different ways in different systems. The faster the memory controller is driven to keep pace with microprocessors, the more memory devices would fail and start to fail. Failure modes include loss of data, and loss of address and control signals. Therefore, a microcomputer system which incorporates faster microprocessor technologies, e.g. 20 or 25 MHz, slower memory device technologies, and still slower input/output (I/O) bus technology, e.g., operating at 8 MHz, is extremely desirable.
While development of memory components such as Dynamic Random Access Memory ("DRAM") devices have usually kept pace with processor technology, often the control logic for these devices does not. Such logic functions and technology were also a limitation on overall microcomputer system speed. For example, in order for the processor to access memory, access signals must be produced in response to bus controller strobe signals which, in turn, are produced in response to access request signals from the microprocessor. Additive overhead associated with both the bus and memory controllers arising from buffering and gate delays is required to produce these signals. Thus, the need is clear for system memory control to be dissociated from the speed of advancing microprocessor technology on the one hand and from conventional or state-of-the-art bus/bus controller technology on the other, not withstanding the high degree of interaction between the processor and system memory.
The speed of operation of microcomputer subsystems is governed by one or more clock or timing signals which may or may not be synchronized. In the past, such clock signals were usually derived from more than one source which was not synchronized. Thus, when synchronized operation of the microprocessor and system memory was required, tolerances in the timing of control, gating and handshake signals had to be relaxed enough to allow for imprecise cooperation of clock signal source. For microcomputers operating at 8 MHz, performance was acceptable and reasonably reliable.
As operating speed is increased, however, critical system timing parameters must be substantially more precise than can be reliably achieved with multi-source clock signals. Thus, for operation at 20 MHz and above, clock signals produced from one source are required to preclude clock and control signal skewing and provide reliable, high-speed operation.
System memory control according to the present invention comprises a synchronous controller for interface with the microprocessor of the designer's choice and an asynchronous memory controller for direct interface with present state-of-the-art input/output (I/O) bus technology such as the Micro Channel Architecture (MCA) manufactured by IBM Corporation. Thus, accessing of 80 nanosecond DRAM available from any number of manufacturers, by either the controller of the present invention, high-speed microprocessors or bus-coupled devices in a microcomputer, a bus timing system having enhanced performance characteristics is facilitated. By dividing system memory control according to the present invention, the evolving technologies of microprocessors and DRAM are anticipated and neither are hampered by the speed of the MCA or pace of development or nature of other conventional bus technology. It is also desirable to have asynchronous memory controller technology for access to memory by bus coupled devices without impacting, i.e., detuning, the performance of either the microprocessor or system memory.
The asynchronous control unit of the present invention provides bus-coupled devices with asynchronous access to a microcomputer system memory in response to control signals from the main I/O bus. Synchronous memory controllers are well known for providing the microprocessor access to system memory in response to command signals from the microprocessor. The present invention may be used to enhance the performance characteristics of the overall microcomputer system by providing separate access to memory for devices and subsystems coupled to the main I/O bus at speeds different from those required by high performance microprocessors. Thus, with the control unit with the present invention, buffering, control signal conditioning or other additive overhead previously required for access to and from system memory by I/O bus-coupled devices via a synchronous memory controller is eliminated. Meta stability problems on the boundary of the synchronous and asynchronous domains are also eliminated.